Recent advances in integrated circuit (IC) technology have created a number of challenges in the design, layout, and fabrication of ICs at the chip level. The availability of sub-quarter micron silicon technologies has permitted the fabrication of millions of logic gates on a single chip. Functions that were previously implemented across multiple chips are now being integrated onto a single chip. Circuit characteristics such as resistance and coupling capacitance, previously second order effects, are now first order effects in the environment of sub-quarter micron silicon technologies. At the same time, the increasingly competitive environment forces manufacturers to bring their chips to market in a shorter time interval. Often, the initial design, layout, and mask fabrication can be very time consuming, even using electronic design automation (EDA) software. Even though the design process is highly automated, it is common to make manual changes to the final layout in order to achieve engineering change orders (ECOs), foundry re-targeting, and yield enhancement.
The design and layout of ICs consists of a number of steps that are performed in a pre-determined order. A general floor plan is first drawn up in which standard cells, taken from a library of cells, are laid out on the chip real estate. Each of these standard cells includes an electronic module or component. After the placement of the standard cells is determined, a routing step is performed in which electrical conductors are laid out or “routed” on the chip in order to interconnect the electronic modules with each other and with peripheral contact pads that are used to connect the IC with external circuitry. Notably, during circuit layout synthesis, routing typically involves the connection of N-Type and P-Type transistors and signal input/output ports using electrical connections and applicable layers according to the electrical connectivity of the circuit being laid out. The applicable layers for interconnection usually include poly-silicon, diffusion, and metal. Routing has a profound effect on the quality of the final compacted cell layout. Bad routing can lead to increased layout errors, poor electrical performance, and low yields.
Following the placement and routing, a series of design rule checks (DRCs) are performed to determine whether any of a number of known design rules have been violated by the final placement and routing. One of these design rules involves so-called “antenna rule violations”. Antenna rule violations are related to a phenomenon in which certain of the routed conductors act as antennas that attract and store an electrical charge that is developed during the manufacturing process, typically during plasma etching.
Plasma etching is a technique widely used in the fabrication of integrated circuits, wherein reactive ions are generated in an ion discharge and accelerated by an electrical field. These ions collide with the wafer surface carrying the semiconductor device being fabricated. The glow discharge used in plasma etching typically results in electrically charging some regions over the wafer surface. This charging can occur in a conductive layer region, for example at a polysilicon gate electrode formed upon the surface of the wafer. A conductive line connected to the gate can act as antenna to accumulate and store a charge, during the etching process. The conductive line facilitates the storage of more charge than would otherwise be stored by the gate electrode. The static charge stored in the conductive lines connected to the gate electrodes of transistors can ultimately discharge through the gate junction, thereby destroying the transistor as well as the IC during the fabrication process. In order to avoid possible damage to the input gates caused by electrostatic discharge due to the antenna effect, protective diodes are sometimes installed at the input gates of transistors. These diodes are referred to as “antenna diodes” since they provide a discharge path to ground for the charges stored by the offending conductive lines.
The “insertion” of antenna diodes in a circuit to correct an antenna rule violation is a very tedious and time-intensive task. The antenna diode insertion process often adds weeks to the design schedule. Conventionally, a layout engineer must run a DRC to identify antenna rule violations and, for each violation, study the layout to locate an area where an antenna diode may be inserted to correct the violation, and re-run the DRC to verify the violation has been removed and no new design rule violations have been introduced. The run-time of this process is very lengthy, often adding weeks or months to the design process. In addition, it is common that design modifications are required several times during the life of a particular product, which may require repetition of the tedious and lengthy antenna diode insertion process.
Accordingly, there exists a need in the art for automatic insertion of antenna diodes for integrated circuits that overcomes the lengthy run-time disadvantages associated with the conventional antenna diode insertion process.